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Job Requirements of Design Verification Engineer:
-
Employment Type:
Full-Time
-
Location:
Austin, TX (Onsite)
Do you meet the requirements for this job?
Design Verification Engineer
Bayone Solutions Inc
Austin, TX (Onsite)
Full-Time
- Local to Austin Market
- No H1B candidate
- Top 2 candidates per suppliers
As a member of our System IP team you will contribute to the functional verification of System IP including coherent interconnect, and executing Test plan
Work with DV team and designers to build verification environments
Develop UVM sequences, tests, scoreboards, monitors and checkers
Write SVA assertions
Functional and Code coverage Closure
Regression triaging and debug
Key Responsibilities Include:
• Define/plan/implement/execute functional verification strategy of complex System IP designs
• Develop feature-based test plans
• Ability to delve into the details of Coherent fabric & LLC design
• Work with DV team and designers to build verification environments
• Develop UVM sequences, tests, scoreboards, monitors and checkers
• Write SVA assertions
Functional and Code coverage Closure
• Regression triaging and debug
• Agility to work on multiple tasks/projects.
Requirements
• BS/MS/PhD (or equivalent experience)
• 12+ years of relevant experience in Verification
• Experience with System Verilog and UVM
• Deep understanding of constrained randomization and the development of efficient test suites
• Proficient in a script language like Perl or Python
• Working knowledge of C++
• Good knowledge of memory subsystem, including interconnect, last-level cache, coherency
• Familiarity of Arm AMBA5 CHI, AMBA4 ACE or AXI coherent interconnect and bus protocols
• Good communication skills and ability & desire to work as a team player are a must.
- No H1B candidate
- Top 2 candidates per suppliers
As a member of our System IP team you will contribute to the functional verification of System IP including coherent interconnect, and executing Test plan
Work with DV team and designers to build verification environments
Develop UVM sequences, tests, scoreboards, monitors and checkers
Write SVA assertions
Functional and Code coverage Closure
Regression triaging and debug
Key Responsibilities Include:
• Define/plan/implement/execute functional verification strategy of complex System IP designs
• Develop feature-based test plans
• Ability to delve into the details of Coherent fabric & LLC design
• Work with DV team and designers to build verification environments
• Develop UVM sequences, tests, scoreboards, monitors and checkers
• Write SVA assertions
Functional and Code coverage Closure
• Regression triaging and debug
• Agility to work on multiple tasks/projects.
Requirements
• BS/MS/PhD (or equivalent experience)
• 12+ years of relevant experience in Verification
• Experience with System Verilog and UVM
• Deep understanding of constrained randomization and the development of efficient test suites
• Proficient in a script language like Perl or Python
• Working knowledge of C++
• Good knowledge of memory subsystem, including interconnect, last-level cache, coherency
• Familiarity of Arm AMBA5 CHI, AMBA4 ACE or AXI coherent interconnect and bus protocols
• Good communication skills and ability & desire to work as a team player are a must.
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