US
0 suggestions are available, use up and down arrow to navigate them
PROCESSING APPLICATION
Hold tight! We’re comparing your resume to the job requirements…
ARE YOU SURE YOU WANT TO APPLY TO THIS JOB?
Based on your Resume, it doesn't look like you meet the requirements from the employer. You can still apply if you think you’re a fit.
Job Requirements of Design Verification Engineer (GPU):
-
Employment Type:
Full-Time
-
Location:
San Jose, CA (Onsite)
Do you meet the requirements for this job?
Design Verification Engineer (GPU)
Bayone Solutions Inc
San Jose, CA (Onsite)
Full-Time
- Local to market in San Jose
- Hybrid onsite 3 days per week (No Remote candidate)
- Knowledge of Block-level (unit level)
- Degubbing and development
- UVM, SystemVerilog exp
- 8 to 10 years of hands-on related exp
Vertical
Technical
Description
As a GPU Design Verification Engineer, your talents will ensure the quality at the heart of our GPU architecture
Creativity is a necessity to overcome the challenges inherent to verifying the proper operation of our low-power GPU
Versatility and broad knowledge of state-of-the-art verification techniques including the most up-to-date IEEE UVM version will place you among the elite within our profession.
Requirements
Role and Responsibilities: Key responsibilities include Work with architects and designers to build verification environments and test plans Craft functional verification coverage strategy to ensure complete test suite implementation Develop assertions and checks to optimize isolation time and produce meaningful failing signatures Analyze failing tests to root cause along, working with RTL and reference modeling teams Provide input on Architectural and Micro-Architectural specifications for testability and accuracy Examine code coverage results, identifying exclusions and improving stimulus Take ownership of key milestone closure by meeting phase gate pass rates, coverage quality, and other quality metrics Skills and Qualifications: Minimum requirements: BS in Computer Engineering, BSEE or comparable and 5+ years of industry experience in a design verification role Proficient in System Verilog/UVM/OVM, and OOP/C++ Deep understanding of constrained randomization and the development of efficient test suites Experience with code coverage and functional coverage-driven verification methodology
Experience in creating, running and debugging of SystemVerilog/UVM constraint-random testbench
Working knowledge of scripting languages such as Python or Perl Understanding of micro-architecture, logic design, FSMs, arithmetic datapath pipelines Preferred qualifications: MS CE/EE with 5+ years of industry experience in verification Good verbal and written communication skills Experience of GPU or CPU is a plus
- Hybrid onsite 3 days per week (No Remote candidate)
- Knowledge of Block-level (unit level)
- Degubbing and development
- UVM, SystemVerilog exp
- 8 to 10 years of hands-on related exp
Vertical
Technical
Description
As a GPU Design Verification Engineer, your talents will ensure the quality at the heart of our GPU architecture
Creativity is a necessity to overcome the challenges inherent to verifying the proper operation of our low-power GPU
Versatility and broad knowledge of state-of-the-art verification techniques including the most up-to-date IEEE UVM version will place you among the elite within our profession.
Requirements
Role and Responsibilities: Key responsibilities include Work with architects and designers to build verification environments and test plans Craft functional verification coverage strategy to ensure complete test suite implementation Develop assertions and checks to optimize isolation time and produce meaningful failing signatures Analyze failing tests to root cause along, working with RTL and reference modeling teams Provide input on Architectural and Micro-Architectural specifications for testability and accuracy Examine code coverage results, identifying exclusions and improving stimulus Take ownership of key milestone closure by meeting phase gate pass rates, coverage quality, and other quality metrics Skills and Qualifications: Minimum requirements: BS in Computer Engineering, BSEE or comparable and 5+ years of industry experience in a design verification role Proficient in System Verilog/UVM/OVM, and OOP/C++ Deep understanding of constrained randomization and the development of efficient test suites Experience with code coverage and functional coverage-driven verification methodology
Experience in creating, running and debugging of SystemVerilog/UVM constraint-random testbench
Working knowledge of scripting languages such as Python or Perl Understanding of micro-architecture, logic design, FSMs, arithmetic datapath pipelines Preferred qualifications: MS CE/EE with 5+ years of industry experience in verification Good verbal and written communication skills Experience of GPU or CPU is a plus
Get job alerts by email.
Sign up now!
Join Our Talent Network!