Memory Controller Designer/RTL Engineer

Notes from the HM Call:
Austin, TX will be preferred. San Jose & San Diego secondary location.
Duration: 6 months

A.Hebbar:

https://www.linkedin.com/in/ akarsh /

• LPDDR & Memory Controller is a must.
• Knowledge of memory controller u-architecture.
• Familiarity with different memory technologies like LPDDR4 /5, HBM.
• Knowledge of JEDEC memory standards preferred.
• Knowledge of AES, ECC, RAS features preferred.
• RTL design
• ASIC design flow would be good to have

10+ yrs of work experience.
1 st round-phone screen of 45mins 1hr.
2 nd round- Panel interview of 2 - 2: 30hrs .- Austin or San Jose- Onsite, San Diego- Virtual


Location: Austin [Preferred], 2nd -San Jose or 3rd -San Diego
- Hybrid 3x per week

Job Description Summary

Samsung is a world leader in Memory, LCD and System LSI technologies that has the vision and commitment to invest in the future of technology demonstrated by the $17B investment in the new 3nm Fab in Texas and the commitment to invest in dramatically expanding design activities across GPU, System IP and SoC Architecture. We are currently looking for exceptional software and hardware engineers to join our System IP team in our Austin, TX R & D Center (SARC) and our Advanced Computing Lab (ACL) in San Jose, CA. Our System IP team develops proprietary coherent interconnect and memory controller deployed in many high volume products.

Job Description
As a senior designer on custom memory controller micro-architect, you will be responsible for working on the micro-architecture development of custom memory controller for LPDDR5, LP. In this role you will be interacting with the system architects, verification, performance/power and design implementation teams. You will be owning and driving the critical memory controller related RTL design, performance and power optimization and also work on logic debug and timing closure of the design. Solid engineer foundation and RTL design experience are desired for success.


Key responsibilities include:

• Drive the timely development and debug of new features on timely development of custom memory controller.
• Working on SOC IP delivery with all sanity checks.
• Work on timing debug and closure.
• Working on LINT, CDC flows and analysis.
• Work on power artist flow and power analysis.
• Working on ECO flows.
• Work with the verification team to verify the functionality and correctness of the design.
• Collaborate with implementation to achieve your timing and area.
• Produce quality RTL on schedule meeting PPA goals
• Engage with performance and power team on achieving performance and power goals.
• Partner with the physical design and CAD team to resolve implementation level details.

Preferred candidate will possess the following:

• PhD, Master's Degree or Bachelor's Degree , Computer Engineer with over 10+ years of experience.
• Strong background owning and driving the RTL design of various sub-blocks of custom memory controller designs
• Demonstrated experience of successful Architectural through RTL design experience on high performance digital designs
• Verilog expertise is required as is a deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis & ECO.
• Knowledge of memory controller u-architecture.
• Familiarity with different memory technologies like LPDDR4/5, HBM.
• Knowledge of JEDEC memory standards preferred.
• Knowledge of AES, ECC, RAS features preferred.
• Strong communication and interpersonal skills are required along with the ability to work in a dynamic, global team.
• Experience with a scripting language like Perl or Python.
• Energetic, curiosity, and passion in logic design.
• Good written and verbal communication skills.